%0 Conference Paper %1 conf/islped/LiangCCCCS19 %A Liang, Yu-Pei %A Chen, Tseng-Yi %A Chang, Yuan-Hao %A Chen, Shuo-Han %A Chen, Pei-Yu %A Shih, Wei-Kuan %B ISLPED %D 2019 %I IEEE %K dblp %P 1-6 %T Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy. %U http://dblp.uni-trier.de/db/conf/islped/islped2019.html#LiangCCCCS19 %@ 978-1-7281-2954-9

@inproceedings{conf/islped/LiangCCCCS19, added-at = {2022-01-03T00:00:00.000+0100}, author = {Liang, Yu-Pei and Chen, Tseng-Yi and Chang, Yuan-Hao and Chen, Shuo-Han and Chen, Pei-Yu and Shih, Wei-Kuan}, biburl = {https://www.bibsonomy.org/bibtex/2c0cf01da3e38aafb1a12336fe6cf1a63/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2019}, ee = {https://doi.org/10.1109/ISLPED.2019.8824899}, interhash = {f80ab0243242b4f7d05de5d60be252d9}, intrahash = {c0cf01da3e38aafb1a12336fe6cf1a63}, isbn = {978-1-7281-2954-9}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2024-04-10T21:21:19.000+0200}, title = {Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2019.html#LiangCCCCS19}, year = 2019 }