%0 Journal Article %1 journals/jssc/WangCLLW10 %A Wang, Jinn-Shyan %A Cheng, Chun-Yuan %A Liu, Je-Ching %A Liu, Yu-Chia %A Wang, Yi-Ming %D 2010 %J IEEE J. Solid State Circuits %K dblp %N 5 %P 1036-1047 %T A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. %U http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#WangCLLW10 %V 45

@article{journals/jssc/WangCLLW10, added-at = {2020-08-30T00:00:00.000+0200}, author = {Wang, Jinn-Shyan and Cheng, Chun-Yuan and Liu, Je-Ching and Liu, Yu-Chia and Wang, Yi-Ming}, biburl = {https://www.bibsonomy.org/bibtex/2d1f282f51a761bb18e72f172b620c33e/dblp}, ee = {https://doi.org/10.1109/JSSC.2010.2047994}, interhash = {fdf13315d62c65312ac6fd37c86603d6}, intrahash = {d1f282f51a761bb18e72f172b620c33e}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 5, pages = {1036-1047}, timestamp = {2020-08-31T11:44:18.000+0200}, title = {A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#WangCLLW10}, volume = 45, year = 2010 }