%0 Conference Paper %1 conf/asicon/Ikeda15 %A Ikeda, Makoto %B ASICON %D 2015 %I IEEE %K dblp %P 1-4 %T Design and optimization of asynchronous circuits with gate-level pipelining. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2015.html#Ikeda15 %@ 978-1-4799-8485-5

@inproceedings{conf/asicon/Ikeda15, added-at = {2018-07-17T00:00:00.000+0200}, author = {Ikeda, Makoto}, biburl = {https://www.bibsonomy.org/bibtex/2952360dba0fe78950f6f4945be809ed1/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2015}, ee = {https://doi.org/10.1109/ASICON.2015.7516956}, interhash = {febf1baad0bcfee5ce23be628c8628b3}, intrahash = {952360dba0fe78950f6f4945be809ed1}, isbn = {978-1-4799-8485-5}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2018-07-18T11:44:51.000+0200}, title = {Design and optimization of asynchronous circuits with gate-level pipelining.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2015.html#Ikeda15}, year = 2015 }