%0 Conference Paper %1 popp:1998:smc %A Popp, Robert L. %A Montana, David J. %A Gassner, Richard R. %A Vidaver, Gordon %A Iyer, Suraj %B IEEE International Conference on Systems, Man, and Cybernetics %C San Diego, CA USA %D 1998 %I IEEE %K CAD, Description FPGA, Hardware Language, VHDL, VHSIC algorithms, arrays, automated circuit configuration description design design, evolution, field gate genetic hardware languages, logic, management, optimisation, programmable programming, requirements, software system variants %P 2184--2189 %T Automated hardware design using genetic programming, VHDL, and FPGAs %V 3 %X We have developed a completely automated approach to hardware design based on integrating three core technologies into one comprehensive system, namely genetic programming (GP), the VHSIC Hardware Description Language (VHDL) and field programmable gate arrays (FPGAs). Our system uses an automated GP engine, as opposed to a human designer, to evolve a hardware design composed of one or more FPGAs that will maximally achieve an application's software requirements. Several variants of our system exist; other variants are currently under development. The focus of this paper is to describe our original system design and its most recent revision to date

@inproceedings{popp:1998:smc, abstract = {We have developed a completely automated approach to hardware design based on integrating three core technologies into one comprehensive system, namely genetic programming (GP), the VHSIC Hardware Description Language (VHDL) and field programmable gate arrays (FPGAs). Our system uses an automated GP engine, as opposed to a human designer, to evolve a hardware design composed of one or more FPGAs that will maximally achieve an application's software requirements. Several variants of our system exist; other variants are currently under development. The focus of this paper is to describe our original system design and its most recent revision to date}, added-at = {2008-06-19T17:46:40.000+0200}, address = {San Diego, CA USA}, author = {Popp, Robert L. and Montana, David J. and Gassner, Richard R. and Vidaver, Gordon and Iyer, Suraj}, biburl = {https://www.bibsonomy.org/bibtex/268879af3375eb231c3fa888955a82307/brazovayeye}, booktitle = {IEEE International Conference on Systems, Man, and Cybernetics}, interhash = {e28b9658039b28e2d046b5a7750b7013}, intrahash = {68879af3375eb231c3fa888955a82307}, keywords = {CAD, Description FPGA, Hardware Language, VHDL, VHSIC algorithms, arrays, automated circuit configuration description design design, evolution, field gate genetic hardware languages, logic, management, optimisation, programmable programming, requirements, software system variants}, month = {11-14 October}, notes = {Inspec Accession Number: 6189463}, pages = {2184--2189}, publisher = {IEEE}, size = {5 pages}, timestamp = {2008-06-19T17:49:51.000+0200}, title = {Automated hardware design using genetic programming, {VHDL}, and {FPGAs}}, volume = 3, year = 1998 }