%0 Journal Article %1 yasunaga:2001:GPEM %A Yasunaga, Moritoshi %A Kim, Jung Hwan %A Yoshihara, Ikuo %D 2001 %J Genetic Programming and Evolvable Machines %K FPGA, MBRTalk NETTalk, VLSI algorithms, design evolvable genetic hardware, methodology, reasoning, %N 3 %P 211--230 %R doi:10.1023/A:1011939025340 %T Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation %V 2 %X In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.

@article{yasunaga:2001:GPEM, abstract = {In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.}, added-at = {2008-06-19T17:35:00.000+0200}, author = {Yasunaga, Moritoshi and Kim, Jung Hwan and Yoshihara, Ikuo}, biburl = {https://www.bibsonomy.org/bibtex/2717e2a28f6b3d1318a20c1fe6356d40d/brazovayeye}, doi = {doi:10.1023/A:1011939025340}, interhash = {c49257bc9de5d9b5a4d378a5938778aa}, intrahash = {717e2a28f6b3d1318a20c1fe6356d40d}, issn = {1389-2576}, journal = {Genetic Programming and Evolvable Machines}, keywords = {FPGA, MBRTalk NETTalk, VLSI algorithms, design evolvable genetic hardware, methodology, reasoning,}, month = {September}, notes = {Article ID: 357592}, number = 3, pages = {211--230}, timestamp = {2008-06-19T17:54:51.000+0200}, title = {Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation}, volume = 2, year = 2001 }