Genetic Programming using Self-Reconfigurable
FPGAs
9th International Workshop on Field Programmable Logic
and Applications, Volume 1673 von LNCS, Seite 301--312. Glasgow, UK, Springer-Verlag, (30 August - 1 September 1998)DOI: doi:10.1007/b72332
Zusammenfassung
FPGA self-reconfiguration for efficient computation in
the context of Genetic Programming (GP). GP involves
evolving programs represented as trees and evaluating
their fitness, the latter operation consuming most of
the time. We present a fast, compact representation of
the tree structures in FPGA logic which can be evolved
as well as executed without external intervention.
Execution of all tree nodes occurs in parallel and is
pipelined. Furthermore, the compact layout enables
multiple trees to execute concurrently, dramatically
speeding up the fitness evaluation phase. An elegant
technique for implementing the evolution phase, made
possible by self-reconfiguration, is also presented. We
use two GP problems as benchmarks to compare the
performance of logic mapped onto a Xilinx XC6264 FPGA
against a software implementation running on a 200 MHz
Pentium Pro PC with 64 MB RAM. Our results show a
speedup of 19 for an arithmetic intensive problem and a
speedup of three orders of magnitude for a logic
operation intensive problem.