Implementation of VLSI Architecture for Lifting Scheme Based DWT
International Journal of Innovative Science and Modern Engineering (IJISME), 1 (12):
20-24 (November 2013)Abstract
To The discrete wavelet transform (DWT) plays a central role in a number of signal and image processing applications. Owing to its importance in real-time signal processing systems, its first hardware implementation has been proposed. Subsequently, significant research effort has been made to optimize DWT/inverse DWT (IDWT) implementation, like architectures based on the folded digit-serial approach and low-complexity architectures with a reduced number of multipliers. However, these hardware architectures do not adequately address the power and area consumption issues, which often are the two most important metrics in today’s high-performance signal processing systems. The main power consuming operation in DWT/IDWT computation is filtering, which requires a significant number of multiplications. The lifting scheme is a new algorithm proposed for the implementation of the wavelet transform. It can reduce the computational complexity of DWT involved with the convolution implementation. Furthermore, the extra memory required to store the results of the convolution can also be reduced by in place computation of the wavelet coefficient with the lifting scheme. The lifting scheme consists of the following three steps associated with the lifting scheme based DWT for the one-dimensional signal:(1) Split step: The input samples are split into even samples and odd samples ,(2) Predict step (P): The even samples are multiplied by the predict factor and then the results are added to the odd samples to generate the detailed coefficients;(3) Update step (U): The detailed coefficients computed by the predict step are multiplied by the update factors and then the results are added to the even samples to get the coarse coefficients. One of the elegant features of the lifting scheme is that the inverse transform is a mirror of the forward transform.