%0 Journal Article %1 journals/tcasII/PeiXLWLH23 %A Pei, Bingxi %A Xu, Shi %A Luo, Zhang %A Wang, Qin %A Lai, Mingche %A He, Weifeng %D 2023 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 10 %P 3787-3791 %T A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII70.html#PeiXLWLH23 %V 70

@article{journals/tcasII/PeiXLWLH23, added-at = {2023-10-14T00:00:00.000+0200}, author = {Pei, Bingxi and Xu, Shi and Luo, Zhang and Wang, Qin and Lai, Mingche and He, Weifeng}, biburl = {https://www.bibsonomy.org/bibtex/21ca85d842cbf11a892ef3cbbd304c8dd/dblp}, ee = {https://doi.org/10.1109/TCSII.2023.3288894}, interhash = {6f26c4a28147812e9fa14cbd64fa79e3}, intrahash = {1ca85d842cbf11a892ef3cbbd304c8dd}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, month = {October}, number = 10, pages = {3787-3791}, timestamp = {2024-04-08T16:53:17.000+0200}, title = {A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII70.html#PeiXLWLH23}, volume = 70, year = 2023 }