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Rapidly Reconfigurable Field-Programmable Gate Arrays for Accelerating Fitness Evaluation in Genetic Programming
Late Breaking Papers at the 1997 Genetic Programming Conference, стр. 121--131. Stanford University, CA, USA, Stanford Bookstore, (13--16 July 1997)
Аннотация
The dominant component of the computational burden of
solving non-trivial problems with evolutionary
algorithms is the task of measuring the fitness of each
individual in each generation of the evolving
population. The advent of rapidly reconfigurable
field-programmable gate arrays (FPGAs) and the idea of
evolvable hardware opens the possiblity of embodying
each individual of the evolving population into
hardware for the purpose of accelerating the
time-consuming fitness evaluation task This paper
demonstrates how the massive parallelism of the rapidly
reconfigurable Xilinx XC6216 FPGA can be exploited to
accelerate the computationally burdensome fitness
evaluation task of genetic programming. The work was
done on Virtual Computing Corporation's low-cost HOTS
expansion board for PC type computers. A 16-step
7-sorter was evolved that has two fewer steps than the
sorting network described in the 1962 O'Connor and
Nelson patent on sorting networks and that has the same
number of steps as the minimal 7-sorter that was
devised by Floyd and Knuth subsequent to the patent.
