%0 Conference Paper %1 conf/itc-asia/WuLR17 %A Wu, Cheng-Hung %A Lee, Kuen-Jong %A Reddy, Sudhakar M. %B ITC-Asia %D 2017 %I IEEE %K dblp %P 21-26 %T Test generation for open and delay faults in CMOS circuits. %U http://dblp.uni-trier.de/db/conf/itc-asia/itc-asia2017.html#WuLR17 %@ 978-1-5386-3051-8

@inproceedings{conf/itc-asia/WuLR17, added-at = {2019-11-13T00:00:00.000+0100}, author = {Wu, Cheng-Hung and Lee, Kuen-Jong and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/2f05b4321a0b8b6b462b12b113964ef52/dblp}, booktitle = {ITC-Asia}, crossref = {conf/itc-asia/2017}, ee = {https://doi.org/10.1109/ITC-ASIA.2017.8097104}, interhash = {7f3d97349031cfdf72129207e58bccc0}, intrahash = {f05b4321a0b8b6b462b12b113964ef52}, isbn = {978-1-5386-3051-8}, keywords = {dblp}, pages = {21-26}, publisher = {IEEE}, timestamp = {2024-04-09T21:38:03.000+0200}, title = {Test generation for open and delay faults in CMOS circuits.}, url = {http://dblp.uni-trier.de/db/conf/itc-asia/itc-asia2017.html#WuLR17}, year = 2017 }