%0 Conference Paper %1 conf/vlsi/SundaresanRV07 %A Sundaresan, Vijay %A Rammohan, Srividhya %A Vemuri, Ranga %B VLSI-SoC %D 2007 %I IEEE %K dblp %P 1-6 %T Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#SundaresanRV07

@inproceedings{conf/vlsi/SundaresanRV07, added-at = {2022-04-09T00:00:00.000+0200}, author = {Sundaresan, Vijay and Rammohan, Srividhya and Vemuri, Ranga}, biburl = {https://www.bibsonomy.org/bibtex/2bbbb58b7026073e5e005bea075fe5528/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2007soc}, ee = {https://doi.org/10.1109/VLSISOC.2007.4402463}, interhash = {b9b986c27589806294fd3b41914aafb2}, intrahash = {bbbb58b7026073e5e005bea075fe5528}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2024-04-10T20:41:12.000+0200}, title = {Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#SundaresanRV07}, year = 2007 }