%0 Journal Article %1 journals/tvlsi/LinDLYCP19 %A Lin, Jai-Ming %A Deng, You-Lun %A Li, Szu-Ting %A Yu, Bo-Heng %A Chang, Li-Yen %A Peng, Te-Wei %D 2019 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 57-68 %T Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#LinDLYCP19 %V 27

@article{journals/tvlsi/LinDLYCP19, added-at = {2020-03-11T00:00:00.000+0100}, author = {Lin, Jai-Ming and Deng, You-Lun and Li, Szu-Ting and Yu, Bo-Heng and Chang, Li-Yen and Peng, Te-Wei}, biburl = {https://www.bibsonomy.org/bibtex/2374f07d43a6162ff727b475511157646/dblp}, ee = {https://doi.org/10.1109/TVLSI.2018.2867833}, interhash = {ccf2ccf137a80245b7e092fcd2f6b5b1}, intrahash = {374f07d43a6162ff727b475511157646}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {57-68}, timestamp = {2020-03-12T11:41:38.000+0100}, title = {Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#LinDLYCP19}, volume = 27, year = 2019 }