%0 Journal Article %1 noauthororeditor %A Chandra, Tanusha Beni Vyas | Shubhash %D 2019 %J International Journal of Trend in Scientific Research and Development %K CMOS Clock Computers Delay Engineering Latch MOSFET Power Product %N 5 %P 1785-1788 %R https://doi.org/10.31142/ijtsrd26707 %T Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology %U https://www.ijtsrd.com/engineering/computer-engineering/26707/comparative-analysis-of-efficient-designs-of-d--latch-using-32nm-cmos-technology/tanusha-beni-vyas %V 3 %X In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Tanusha Beni Vyas | Shubhash Chandra "Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd) ISSN: 2456-6470 Volume-3 | Issue-5 August 2019 URL: https://www.ijtsrd.com/papers/ijtsrd26707.pdfPaper URL: https://www.ijtsrd.com/engineering/computer-engineering/26707/comparative-analysis-of-efficient-designs-of-d--latch-using-32nm-cmos-technology/tanusha-beni-vyas

@article{noauthororeditor, abstract = {In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Tanusha Beni Vyas | Shubhash Chandra "Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd) ISSN: 2456-6470 Volume-3 | Issue-5 August 2019 URL: https://www.ijtsrd.com/papers/ijtsrd26707.pdfPaper URL: https://www.ijtsrd.com/engineering/computer-engineering/26707/comparative-analysis-of-efficient-designs-of-d--latch-using-32nm-cmos-technology/tanusha-beni-vyas }, added-at = {2019-09-12T12:16:48.000+0200}, author = {Chandra, Tanusha Beni Vyas | Shubhash}, biburl = {https://www.bibsonomy.org/bibtex/24133ae796ea83801e557b5709adfe501/ijtsrd}, doi = {https://doi.org/10.31142/ijtsrd26707}, interhash = {dacb6d0de8061037c3e213a9bd0455ca}, intrahash = {4133ae796ea83801e557b5709adfe501}, issn = {2456-6470}, journal = {International Journal of Trend in Scientific Research and Development}, keywords = {CMOS Clock Computers Delay Engineering Latch MOSFET Power Product}, language = {English}, month = aug, number = 5, pages = {1785-1788}, timestamp = {2019-09-12T12:16:48.000+0200}, title = {Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology }, url = {https://www.ijtsrd.com/engineering/computer-engineering/26707/comparative-analysis-of-efficient-designs-of-d--latch-using-32nm-cmos-technology/tanusha-beni-vyas}, volume = 3, year = 2019 }