%0 Journal Article %1 journals/ieicet/NakasatoOSF07 %A Nakasato, Masato %A Ohtake, Satoshi %A Saluja, Kewal K. %A Fujiwara, Hideo %D 2007 %J IEICE Trans. Inf. Syst. %K dblp %N 1 %P 296-305 %T Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet90d.html#NakasatoOSF07 %V 90-D

@article{journals/ieicet/NakasatoOSF07, added-at = {2020-04-11T00:00:00.000+0200}, author = {Nakasato, Masato and Ohtake, Satoshi and Saluja, Kewal K. and Fujiwara, Hideo}, biburl = {https://www.bibsonomy.org/bibtex/284682b779d7323a53949e26ab0dc38cd/dblp}, ee = {https://doi.org/10.1093/ietisy/e90-1.1.296}, interhash = {ea9e91307ac5b8681c5133f1c06673be}, intrahash = {84682b779d7323a53949e26ab0dc38cd}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 1, pages = {296-305}, timestamp = {2020-04-14T11:56:06.000+0200}, title = {Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet90d.html#NakasatoOSF07}, volume = {90-D}, year = 2007 }