Author of the publication

High-frequency characterization of on-chip digital interconnects.

, , , , , , and . IEEE J. Solid State Circuits, 37 (6): 716-725 (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Supply and threshold voltage scaling for low power CMOS., , and . IEEE J. Solid State Circuits, 32 (8): 1210-1216 (1997)Circuits and techniques for high-resolution measurement of on-chip power supply noise., , and . IEEE J. Solid State Circuits, 40 (4): 820-828 (2005)Low-power SRAM design using half-swing pulse-mode techniques., , , , , , , , and . IEEE J. Solid State Circuits, 33 (11): 1659-1671 (1998)A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation., and . IEEE J. Solid State Circuits, 35 (11): 1619-1628 (2000)Time-Variant Characterization and Compensation of Wideband Circuits., , , and . CICC, page 487-490. IEEE, (2007)Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver., , and . ICC, page 1934-1939. IEEE, (2002)Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links., , , and . ICC, page 2693-2698. IEEE, (2007)A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages., and . IEEE Symposium on Computer Arithmetic, page 210-217. IEEE, (1991)Rounding algorithms for IEEE multipliers., , and . IEEE Symposium on Computer Arithmetic, page 176-183. IEEE, (1989)Leveraging designer's intent: A path toward simpler analog CAD tools., , , and . CICC, page 613-620. IEEE, (2009)