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Disambiguation of "Makino, Hiroshi"

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, , , , and . IEEE J. Solid State Circuits, 32 (2): 293 (1997)

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Hiroshi Kawabe

Hiroshi Murata

Hiroshi Kubota

Hiroshi Uchida

Hiroshi Fukuzaki

 

Other publications of authors with the same name

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield., , , , , , , and . IET Circuits Devices Syst., 6 (4): 260-270 (2012)Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply., , , , , , and . IEEE J. Solid State Circuits, 32 (2): 292 (1997)Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2194-2203 (2014)Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 230-234 (2011)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 43 (1): 96-108 (2008)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , and . ISCAS (1), page 73-76. IEEE, (2005)Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology., , , , , and . ISLPED, page 15-20. ACM, (2008)Authors Reply., , , , and . IEEE J. Solid State Circuits, 32 (2): 293 (1997)The Challenge of Collaboration among Academies and Asia Pacific for ITS R&D., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (1): 259-266 (2015)