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Quasi-3D simulation approach for comparative evaluation of triggering ESD protection structures., , , and . Microelectron. Reliab., 43 (3): 427-437 (2003)RF ESD protection strategies - the design and performance trade-off challenges., , , , , , , , , and 5 other author(s). CICC, page 489-496. IEEE, (2005)A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits., , , , , , , , , and 2 other author(s). Microelectron. Reliab., 44 (9-11): 1885-1890 (2004)Voltage Acceleration of Power NLDMOS Hot Carrier Degradation., and . IRPS, page 1-4. IEEE, (2023)ESD Avalanche Diodes Degradation in EOS Regime., and . IRPS, page 1-4. IEEE, (2023)LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits., , , and . Microelectron. Reliab., 43 (1): 61-69 (2003)Bipolar SCR ESD devices., and . Microelectron. Reliab., 45 (3-4): 457-471 (2005)Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes., , , and . Microelectron. Reliab., 51 (12): 2015-2030 (2011)ESD circuit model based protection network optimisation for extended-voltage NMOS drivers., , , , and . Microelectron. Reliab., 45 (9-11): 1430-1435 (2005)