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Jitter-Power Trade-Offs in PLLs.. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (4): 1381-1387 (2021)A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector., and . IEEE J. Solid State Circuits, 38 (1): 13-21 (2003)Design techniques for low-voltage high-speed digital bipolar circuits., , and . IEEE J. Solid State Circuits, 29 (3): 332-339 (March 1994)40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology., and . IEEE J. Solid State Circuits, 39 (12): 2389-2396 (2004)A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance., and . IEEE J. Solid State Circuits, 57 (9): 2856-2867 (2022)10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology., and . IEEE J. Solid State Circuits, 38 (12): 2138-2146 (2003)A Low-Power CMOS Receiver for 5 GHz WLAN., and . IEEE J. Solid State Circuits, 50 (3): 630-643 (2015)A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25fREF., and . IEEE J. Solid State Circuits, 53 (6): 1707-1718 (2018)A New Transceiver Architecture for the 60-GHz Band., and . IEEE J. Solid State Circuits, 44 (3): 751-762 (2009)Analysis of Metastability in Pipelined ADCs., and . IEEE J. Solid State Circuits, 49 (5): 1198-1209 (2014)