( en | de | ru )

 

Disambiguation of "Gurunarayanan, S."

Author of the publication

copydeleteadd this publication to your clipboard
An efficient method to compute static single assignment form for multicore architecture.

, , , and . RAIT, page 776-781. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

S Danischewski

S Hilt

S Ulrich

S Bachmann

S Hüttelmaier

 

Other publications of authors with the same name

A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT., , and . J. Intell. Fuzzy Syst., 36 (5): 4531-4543 (2019)Integrated Cooperative Synchronization for Wireless Sensor Networks., , , and . IEEE Wirel. Commun. Lett., 8 (3): 701-704 (2019)Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array., , , and . VDAT, page 1-4. IEEE, (2020)A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications., , , and . Integr., (2019)Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems., , , and . ICDCN, volume 4308 of Lecture Notes in Computer Science, page 466-478. Springer, (2006)A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm., , , and . VLSID, page 300-305. IEEE Computer Society, (2014)An efficient method to compute static single assignment form for multicore architecture., , , and . RAIT, page 776-781. IEEE, (2012)Global Scheduling Heuristics for Multicore Architecture., , , and . Sci. Program., (2015)An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors., , and . J. Supercomput., 71 (10): 3904-3933 (2015)Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications., , , , and . J. Circuits Syst. Comput., 30 (4): 2150058:1-2150058:14 (2021)