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Disambiguation of "Nakamura, Tadao"

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Design of a low power NoC router using Marching Memory Through type.

, , , , , , , and . NOCS, page 111-118. IEEE, (2014)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Hideki Nakamura

Hatsuo Nakamura

 

Other publications of authors with the same name

Exploiting Loop-Level Parallelism with the Shift Architecture., and . SBAC-PAD, page 184-194. IEEE Computer Society, (2002)An Adaptive Network Routing Method by Electrical-Circuit Modeling., , and . INFOCOM, page 586-592. IEEE Computer Society, (1993)Toward Architecting and Designing Novel Computers.. Asia-Pacific Computer Systems Architecture Conference, volume 2823 of Lecture Notes in Computer Science, page 8-13. Springer, (2003)Automated Design of Wave Pipelined Multiport Register Files., , , , and . ASP-DAC, page 197-202. IEEE, (1998)Panel discussions: "Cool chips for the next decade"., , , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2017)A low power NoC router using the marching memory through type., , , , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2014)On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck., , , , and . NOCS, page 16:1-16:8. ACM, (2015)The Convergence of Asynchronous Iterations for the Fixed Point of a Splitting Operator., and . Parallel Algorithms Appl., 7 (3-4): 229-235 (1995)Efficient parallel processing of competitive learning algorithms., , , , and . Parallel Comput., 30 (12): 1361-1383 (2004)Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks., , , , , , and . IASTED PDCS, page 578-582. IASTED/ACTA Press, (2002)