%0 Journal Article %1 journals/tcas/KoYKOPJ17 %A Ko, Junyoung %A Yang, Younghwi %A Kim, Jisu %A Oh, Younghoon %A Park, Hyun Kook %A Jung, Seong-Ook %D 2017 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 6 %P 1444-1455 %T Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI64.html#KoYKOPJ17 %V 64-I

@article{journals/tcas/KoYKOPJ17, added-at = {2021-04-14T00:00:00.000+0200}, author = {Ko, Junyoung and Yang, Younghwi and Kim, Jisu and Oh, Younghoon and Park, Hyun Kook and Jung, Seong-Ook}, biburl = {https://www.bibsonomy.org/bibtex/24de95e7b1fbd1c04a61057f4bd2dcf07/dblp}, ee = {https://doi.org/10.1109/TCSI.2017.2654270}, interhash = {01a093181465288afe48bd8662d25a94}, intrahash = {4de95e7b1fbd1c04a61057f4bd2dcf07}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 6, pages = {1444-1455}, timestamp = {2024-04-09T06:12:48.000+0200}, title = {Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI64.html#KoYKOPJ17}, volume = {64-I}, year = 2017 }