%0 Conference Paper %1 conf/vlsic/ChoCJOOKKCSSJ21 %A Cho, Keonhee %A Choi, Heekyung %A Jung, In Jun %A Oh, Ji Sang %A Oh, Tae Woo %A Kim, Ki-Ryong %A Kim, Giseok %A Choi, Taemin %A Sim, Changsoo %A Song, Taejoong %A Jung, Seong-Ook %B VLSI Circuits %D 2021 %I IEEE %K dblp %P 1-2 %T SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#ChoCJOOKKCSSJ21 %@ 978-4-86348-780-2

@inproceedings{conf/vlsic/ChoCJOOKKCSSJ21, added-at = {2021-10-14T00:00:00.000+0200}, author = {Cho, Keonhee and Choi, Heekyung and Jung, In Jun and Oh, Ji Sang and Oh, Tae Woo and Kim, Ki-Ryong and Kim, Giseok and Choi, Taemin and Sim, Changsoo and Song, Taejoong and Jung, Seong-Ook}, biburl = {https://www.bibsonomy.org/bibtex/28d673b18c2fac5d39fea9bfaf6fa161f/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2021}, ee = {https://doi.org/10.23919/VLSICircuits52068.2021.9492505}, interhash = {0866ab4aa5d1150fdd80b1451fbfee8d}, intrahash = {8d673b18c2fac5d39fea9bfaf6fa161f}, isbn = {978-4-86348-780-2}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T21:13:43.000+0200}, title = {SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#ChoCJOOKKCSSJ21}, year = 2021 }