%0 Conference Paper %1 conf/icecsys/YesilSY19 %A Yesil, Soner %A Sen, Cansu %A Yilmaz, Ali Özgür %B ICECS %D 2019 %I IEEE %K dblp %P 614-617 %T Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion. %U http://dblp.uni-trier.de/db/conf/icecsys/icecsys2019.html#YesilSY19 %@ 978-1-7281-0996-1

@inproceedings{conf/icecsys/YesilSY19, added-at = {2020-02-03T00:00:00.000+0100}, author = {Yesil, Soner and Sen, Cansu and Yilmaz, Ali Özgür}, biburl = {https://www.bibsonomy.org/bibtex/2a99d1c21ffbbbf805faa12ccb3e46868/dblp}, booktitle = {ICECS}, crossref = {conf/icecsys/2019}, ee = {https://doi.org/10.1109/ICECS46596.2019.8964743}, interhash = {03af67576eb3af45f32194c55a01a50e}, intrahash = {a99d1c21ffbbbf805faa12ccb3e46868}, isbn = {978-1-7281-0996-1}, keywords = {dblp}, pages = {614-617}, publisher = {IEEE}, timestamp = {2020-02-04T11:43:13.000+0100}, title = {Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion.}, url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2019.html#YesilSY19}, year = 2019 }