%0 Conference Paper %1 conf/iccS/ChenS16a %A Chen, Shaolong %A Senar, Miquel A. %B ICCS %D 2016 %E Connolly, Michelle %I Elsevier %K dblp %P 2438-2442 %T Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. %U http://dblp.uni-trier.de/db/conf/iccS/iccS2016.html#ChenS16a %V 80

@inproceedings{conf/iccS/ChenS16a, added-at = {2017-08-23T00:00:00.000+0200}, author = {Chen, Shaolong and Senar, Miquel A.}, biburl = {https://www.bibsonomy.org/bibtex/2cfa908b351a19d3eaf03788c28fe1320/dblp}, booktitle = {ICCS}, crossref = {conf/iccS/2016}, editor = {Connolly, Michelle}, ee = {https://doi.org/10.1016/j.procs.2016.05.544}, interhash = {03c021ead75153c20a732734e5dd6416}, intrahash = {cfa908b351a19d3eaf03788c28fe1320}, keywords = {dblp}, pages = {2438-2442}, publisher = {Elsevier}, series = {Procedia Computer Science}, timestamp = {2017-08-24T11:42:28.000+0200}, title = {Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures.}, url = {http://dblp.uni-trier.de/db/conf/iccS/iccS2016.html#ChenS16a}, volume = 80, year = 2016 }