%0 Conference Paper %1 conf/aPcsac/ZhangZZX06 %A Zhang, Chengyi %A Zhou, Hongwei %A Zhang, Minxuan %A Xing, Zuocheng %B Asia-Pacific Computer Systems Architecture Conference %D 2006 %E Jesshope, Chris R. %E Egan, Colin %I Springer %K dblp %P 588-594 %T An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. %U http://dblp.uni-trier.de/db/conf/aPcsac/aPcsac2006.html#ZhangZZX06 %V 4186 %@ 3-540-40056-7

@inproceedings{conf/aPcsac/ZhangZZX06, added-at = {2017-05-24T00:00:00.000+0200}, author = {Zhang, Chengyi and Zhou, Hongwei and Zhang, Minxuan and Xing, Zuocheng}, biburl = {https://www.bibsonomy.org/bibtex/2cce7c894c9b35b6bd52b06b6dee81733/dblp}, booktitle = {Asia-Pacific Computer Systems Architecture Conference}, crossref = {conf/aPcsac/2006}, editor = {Jesshope, Chris R. and Egan, Colin}, ee = {https://doi.org/10.1007/11859802_62}, interhash = {0771246a468dd459d26a3b62cc3f4d0e}, intrahash = {cce7c894c9b35b6bd52b06b6dee81733}, isbn = {3-540-40056-7}, keywords = {dblp}, pages = {588-594}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-05-15T17:18:32.000+0200}, title = {An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.}, url = {http://dblp.uni-trier.de/db/conf/aPcsac/aPcsac2006.html#ZhangZZX06}, volume = 4186, year = 2006 }