%0 Conference Paper %1 conf/isocc/RohLLS21 %A Roh, Jae Hong %A Lee, Useok %A Lee, Yongje %A Sunwoo, Myung Hoon %B ISOCC %D 2021 %I IEEE %K dblp %P 19-20 %T Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder. %U http://dblp.uni-trier.de/db/conf/isocc/isocc2021.html#RohLLS21 %@ 978-1-6654-0174-6

@inproceedings{conf/isocc/RohLLS21, added-at = {2021-12-06T00:00:00.000+0100}, author = {Roh, Jae Hong and Lee, Useok and Lee, Yongje and Sunwoo, Myung Hoon}, biburl = {https://www.bibsonomy.org/bibtex/234fea0f51b8c61eb94fd26e95a06a6e8/dblp}, booktitle = {ISOCC}, crossref = {conf/isocc/2021}, ee = {https://doi.org/10.1109/ISOCC53507.2021.9613860}, interhash = {07cc572d5c70b87c569c7295a012e6fb}, intrahash = {34fea0f51b8c61eb94fd26e95a06a6e8}, isbn = {978-1-6654-0174-6}, keywords = {dblp}, pages = {19-20}, publisher = {IEEE}, timestamp = {2024-04-09T23:34:13.000+0200}, title = {Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder.}, url = {http://dblp.uni-trier.de/db/conf/isocc/isocc2021.html#RohLLS21}, year = 2021 }