Inproceedings,
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL.
Y. Zhang, B. Liu, X. Gu, C. Wang, K. Yanagisawa, J. Qiu, Y. Wang, J. Pang, A. Shirane, and K. Okada.VLSI Circuits, page 1-2. IEEE, (2020)
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- VLSI Circuits
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- 2020
- pages
- 1-2
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- ee
- https://doi.org/10.1109/VLSICircuits18222.2020.9162955
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- 978-1-7281-9942-9
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- http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#ZhangLGWYQWPSO20
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%1 conf/vlsic/ZhangLGWYQWPSO20
%A Zhang, Yuncheng
%A Liu, Bangan
%A Gu, Xiaofan
%A Wang, Chun
%A Yanagisawa, Kiyoshi
%A Qiu, Junjun
%A Wang, Yun
%A Pang, Jian
%A Shirane, Atsushi
%A Okada, Kenichi
%B VLSI Circuits
%D 2020
%I IEEE
%K dblp
%P 1-2
%T A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL.
%U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#ZhangLGWYQWPSO20
%@ 978-1-7281-9942-9
@inproceedings{conf/vlsic/ZhangLGWYQWPSO20,
added-at = {2021-04-09T00:00:00.000+0200},
author = {Zhang, Yuncheng and Liu, Bangan and Gu, Xiaofan and Wang, Chun and Yanagisawa, Kiyoshi and Qiu, Junjun and Wang, Yun and Pang, Jian and Shirane, Atsushi and Okada, Kenichi},
biburl = {https://www.bibsonomy.org/bibtex/22001da2d8cbfe496d04ffb597fc3f584/dblp},
booktitle = {VLSI Circuits},
crossref = {conf/vlsic/2020},
ee = {https://doi.org/10.1109/VLSICircuits18222.2020.9162955},
interhash = {088883e3da8a5f90c266777305afa612},
intrahash = {2001da2d8cbfe496d04ffb597fc3f584},
isbn = {978-1-7281-9942-9},
keywords = {dblp},
pages = {1-2},
publisher = {IEEE},
timestamp = {2024-04-10T15:34:38.000+0200},
title = {A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL.},
url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#ZhangLGWYQWPSO20},
year = 2020
}