%0 Journal Article %1 journals/jssc/DevlinIA11 %A Devlin, Benjamin Stefan %A Ikeda, Makoto %A Asada, Kunihiro %D 2011 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 2500-2513 %T A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. %U http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#DevlinIA11 %V 46

@article{journals/jssc/DevlinIA11, added-at = {2020-08-30T00:00:00.000+0200}, author = {Devlin, Benjamin Stefan and Ikeda, Makoto and Asada, Kunihiro}, biburl = {https://www.bibsonomy.org/bibtex/2e977fc13ea3bd2c3d02e1c7f63bca1bc/dblp}, ee = {https://doi.org/10.1109/JSSC.2011.2164024}, interhash = {08df099632bdb4e39965fe0d2b1da062}, intrahash = {e977fc13ea3bd2c3d02e1c7f63bca1bc}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {2500-2513}, timestamp = {2020-08-31T11:40:31.000+0200}, title = {A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#DevlinIA11}, volume = 46, year = 2011 }