Inproceedings,
Tackling memory access latency through DRAM row management.
S. Srikanth, L. Subramanian, S. Subramoney, T. Conte, and H. Wang.MEMSYS, page 137-147. ACM, (2018)
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- BibTeX key
- conf/memsys/SrikanthSSCW18
- entry type
- inproceedings
- booktitle
- MEMSYS
- year
- 2018
- pages
- 137-147
- publisher
- ACM
- crossref
- conf/memsys/2018
- ee
- https://doi.org/10.1145/3240302.3240314
- isbn
- 978-1-4503-6475-1
- url
- http://dblp.uni-trier.de/db/conf/memsys/memsys2018.html#SrikanthSSCW18
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- please select -%0 Conference Paper
%1 conf/memsys/SrikanthSSCW18
%A Srikanth, Sriseshan
%A Subramanian, Lavanya
%A Subramoney, Sreenivas
%A Conte, Thomas M.
%A Wang, Hong
%B MEMSYS
%D 2018
%E Jacob, Bruce L.
%I ACM
%K dblp
%P 137-147
%T Tackling memory access latency through DRAM row management.
%U http://dblp.uni-trier.de/db/conf/memsys/memsys2018.html#SrikanthSSCW18
%@ 978-1-4503-6475-1
@inproceedings{conf/memsys/SrikanthSSCW18,
added-at = {2021-10-14T00:00:00.000+0200},
author = {Srikanth, Sriseshan and Subramanian, Lavanya and Subramoney, Sreenivas and Conte, Thomas M. and Wang, Hong},
biburl = {https://www.bibsonomy.org/bibtex/24cccaa7d1b38aad5a6cb6fc62a2f7222/dblp},
booktitle = {MEMSYS},
crossref = {conf/memsys/2018},
editor = {Jacob, Bruce L.},
ee = {https://doi.org/10.1145/3240302.3240314},
interhash = {09bfc8b1e94b49ae9cd9301f3a899f95},
intrahash = {4cccaa7d1b38aad5a6cb6fc62a2f7222},
isbn = {978-1-4503-6475-1},
keywords = {dblp},
pages = {137-147},
publisher = {ACM},
timestamp = {2024-04-10T20:28:02.000+0200},
title = {Tackling memory access latency through DRAM row management.},
url = {http://dblp.uni-trier.de/db/conf/memsys/memsys2018.html#SrikanthSSCW18},
year = 2018
}