%0 Journal Article %1 journals/jssc/DaneshHFRH13 %A Danesh, Seyed %A Hurwitz, Jed %A Findlater, Keith %A Renshaw, David R. %A Henderson, Robert K. %D 2013 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 733-748 %T A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design. %U http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#DaneshHFRH13 %V 48

@article{journals/jssc/DaneshHFRH13, added-at = {2020-08-30T00:00:00.000+0200}, author = {Danesh, Seyed and Hurwitz, Jed and Findlater, Keith and Renshaw, David R. and Henderson, Robert K.}, biburl = {https://www.bibsonomy.org/bibtex/2e76506dc17688f0d2a38658a29ca0598/dblp}, ee = {https://doi.org/10.1109/JSSC.2013.2237672}, interhash = {09e1ed982bb73cb5ec1f265e55a02cc8}, intrahash = {e76506dc17688f0d2a38658a29ca0598}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 3, pages = {733-748}, timestamp = {2020-08-31T11:42:56.000+0200}, title = {A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#DaneshHFRH13}, volume = 48, year = 2013 }