%0 Journal Article %1 journals/jssc/VarzaghaniY09 %A Varzaghani, Aida %A Yang, Chih-Kong Ken %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 901-915 %T A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#VarzaghaniY09 %V 44

@article{journals/jssc/VarzaghaniY09, added-at = {2020-08-30T00:00:00.000+0200}, author = {Varzaghani, Aida and Yang, Chih-Kong Ken}, biburl = {https://www.bibsonomy.org/bibtex/240b5700b716170cbc2427b14bd536c04/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2013765}, interhash = {0d8d7b417e0d05d321ea0b1591cb9e4e}, intrahash = {40b5700b716170cbc2427b14bd536c04}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 3, pages = {901-915}, timestamp = {2020-08-31T11:41:10.000+0200}, title = {A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#VarzaghaniY09}, volume = 44, year = 2009 }