%0 Conference Paper %1 conf/imw2/FengJQZKKCSLYHZ23 %A Feng, Daohuan %A Jiang, Yi %A Qiu, Yunsong %A Zheng, Yuhong %A Kim, Harry %A Kim, Jaewoo %A Chu, Jian %A Shao, Guangsu %A Liao, Yucheng %A Yang, Chen %A Hu, Minrui %A Zhao, Wenli %A Xia, Linjiang %A Xiao, Jianfeng %A Ma, Di %A Cheng, Yuan %A Kong, Xiangbo %A Lin, Chao %A Li, Tianming %A Li, Yongjie %A Meng, Jingheng %A Shao, Kai %A Wang, Yan %A Yang, Xiaoan %A Liu, Xiang %A Han, Qinghua %A Li, Huiming %A Tang, Yanzhe %A Liu, Mingde %A Wu, Eric %A Li, Xiaoping %A Huang, Renrui %A Zhang, Mingtang %A Hou, Long %A Pan, Xuan %A Jin, Xinwen %A Zhao, Shuiping %A Han, Dh %A Park, Ted %A Xiao, Deyuan %A Zhao, Chao %A Yoo, Abraham %B IMW %D 2023 %I IEEE %K dblp %P 1-4 %T Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture. %U http://dblp.uni-trier.de/db/conf/imw2/imw2023.html#FengJQZKKCSLYHZ23 %@ 978-1-6654-7459-7

@inproceedings{conf/imw2/FengJQZKKCSLYHZ23, added-at = {2024-03-21T00:00:00.000+0100}, author = {Feng, Daohuan and Jiang, Yi and Qiu, Yunsong and Zheng, Yuhong and Kim, Harry and Kim, Jaewoo and Chu, Jian and Shao, Guangsu and Liao, Yucheng and Yang, Chen and Hu, Minrui and Zhao, Wenli and Xia, Linjiang and Xiao, Jianfeng and Ma, Di and Cheng, Yuan and Kong, Xiangbo and Lin, Chao and Li, Tianming and Li, Yongjie and Meng, Jingheng and Shao, Kai and Wang, Yan and Yang, Xiaoan and Liu, Xiang and Han, Qinghua and Li, Huiming and Tang, Yanzhe and Liu, Mingde and Wu, Eric and Li, Xiaoping and Huang, Renrui and Zhang, Mingtang and Hou, Long and Pan, Xuan and Jin, Xinwen and Zhao, Shuiping and Han, Dh and Park, Ted and Xiao, Deyuan and Zhao, Chao and Yoo, Abraham}, biburl = {https://www.bibsonomy.org/bibtex/2d3b9c3d04ae21faf9ee15acb9c6c9fbe/dblp}, booktitle = {IMW}, crossref = {conf/imw2/2023}, ee = {https://doi.org/10.1109/IMW56887.2023.10145977}, interhash = {0f536f8b40197bed998d9819def05b18}, intrahash = {d3b9c3d04ae21faf9ee15acb9c6c9fbe}, isbn = {978-1-6654-7459-7}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2024-04-09T19:34:03.000+0200}, title = {Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture.}, url = {http://dblp.uni-trier.de/db/conf/imw2/imw2023.html#FengJQZKKCSLYHZ23}, year = 2023 }