%0 Conference Paper %1 conf/fdl/PavlenkoWSKWK08a %A Pavlenko, Evgeny %A Wedler, Markus %A Stoffel, Dominik %A Kunz, Wolfgang %A Wienand, Oliver %A Karibaev, Evgeny %B FDL (Selected Papers) %D 2008 %E Radetzki, Martin %K dblp %P 257-272 %T A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level. %U http://dblp.uni-trier.de/db/conf/fdl/fdl2008s.html#PavlenkoWSKWK08a %V 36

@inproceedings{conf/fdl/PavlenkoWSKWK08a, added-at = {2019-02-21T00:00:00.000+0100}, author = {Pavlenko, Evgeny and Wedler, Markus and Stoffel, Dominik and Kunz, Wolfgang and Wienand, Oliver and Karibaev, Evgeny}, biburl = {https://www.bibsonomy.org/bibtex/27db37deccfcf96f90ecfdb251fdf69cf/dblp}, booktitle = {FDL (Selected Papers)}, crossref = {conf/fdl/2008s}, editor = {Radetzki, Martin}, ee = {https://doi.org/10.1007/978-1-4020-9714-0_17}, interhash = {0f6c366f791d5008cf56a298073c57d0}, intrahash = {7db37deccfcf96f90ecfdb251fdf69cf}, keywords = {dblp}, pages = {257-272}, series = {Lecture Notes in Electrical Engineering}, timestamp = {2019-02-26T11:37:47.000+0100}, title = {A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level.}, url = {http://dblp.uni-trier.de/db/conf/fdl/fdl2008s.html#PavlenkoWSKWK08a}, volume = 36, year = 2008 }