%0 Conference Paper %1 conf/vlsi-dat/ZhangZRW19 %A Zhang, Yining %A Zhao, Jiahao %A Rhee, Woogeun %A Wang, Zhihua %B VLSI-DAT %D 2019 %I IEEE %K dblp %P 1-4 %T Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2019.html#ZhangZRW19 %@ 978-1-7281-0655-7

@inproceedings{conf/vlsi-dat/ZhangZRW19, added-at = {2022-04-09T00:00:00.000+0200}, author = {Zhang, Yining and Zhao, Jiahao and Rhee, Woogeun and Wang, Zhihua}, biburl = {https://www.bibsonomy.org/bibtex/2ff2683896941586acad45d854c246124/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2019}, ee = {https://doi.org/10.1109/VLSI-DAT.2019.8741607}, interhash = {0f8361a5717dd6f95a447346edf4d78b}, intrahash = {ff2683896941586acad45d854c246124}, isbn = {978-1-7281-0655-7}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2024-04-10T19:50:02.000+0200}, title = {Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2019.html#ZhangZRW19}, year = 2019 }