%0 Conference Paper %1 conf/irps/NarasimhamCWB19 %A Narasimham, Balaji %A Chandrasekharan, K. %A Wang, J. K. %A Bhuva, Bharat L. %B IRPS %D 2019 %I IEEE %K dblp %P 1-4 %T Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. %U http://dblp.uni-trier.de/db/conf/irps/irps2019.html#NarasimhamCWB19 %@ 978-1-5386-9504-3

@inproceedings{conf/irps/NarasimhamCWB19, added-at = {2019-05-31T00:00:00.000+0200}, author = {Narasimham, Balaji and Chandrasekharan, K. and Wang, J. K. and Bhuva, Bharat L.}, biburl = {https://www.bibsonomy.org/bibtex/20efe949f78063fa5b85441b18f5990d3/dblp}, booktitle = {IRPS}, crossref = {conf/irps/2019}, ee = {https://doi.org/10.1109/IRPS.2019.8720408}, interhash = {1189f1ad864181e83d462b13bb73e5eb}, intrahash = {0efe949f78063fa5b85441b18f5990d3}, isbn = {978-1-5386-9504-3}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T14:45:22.000+0200}, title = {Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.}, url = {http://dblp.uni-trier.de/db/conf/irps/irps2019.html#NarasimhamCWB19}, year = 2019 }