%0 Conference Paper %1 conf/vlsi/BrusamarelloSWR07 %A Brusamarello, Lucas %A da Silva, Roberto %A Wirth, Gilson I. %A Reis, Ricardo A. L. %B VLSI-SoC %D 2007 %I IEEE %K dblp %P 94-98 %T Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#BrusamarelloSWR07

@inproceedings{conf/vlsi/BrusamarelloSWR07, added-at = {2021-10-14T00:00:00.000+0200}, author = {Brusamarello, Lucas and da Silva, Roberto and Wirth, Gilson I. and Reis, Ricardo A. L.}, biburl = {https://www.bibsonomy.org/bibtex/247913dcfbad3815a8d7711435dcc9f61/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2007soc}, ee = {https://doi.org/10.1109/VLSISOC.2007.4402479}, interhash = {123efd4fd3e83ef7c85fb35ee129f9a1}, intrahash = {47913dcfbad3815a8d7711435dcc9f61}, keywords = {dblp}, pages = {94-98}, publisher = {IEEE}, timestamp = {2024-04-10T20:41:12.000+0200}, title = {Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#BrusamarelloSWR07}, year = 2007 }