%0 Conference Paper %1 conf/asscc/ZimmerCNA16 %A Zimmer, Brian %A Chiu, Pi-Feng %A Nikolic, Borivoje %A Asanovic, Krste %B A-SSCC %D 2016 %I IEEE %K dblp %P 121-124 %T Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. %U http://dblp.uni-trier.de/db/conf/asscc/asscc2016.html#ZimmerCNA16 %@ 978-1-5090-3700-1

@inproceedings{conf/asscc/ZimmerCNA16, added-at = {2023-06-26T00:00:00.000+0200}, author = {Zimmer, Brian and Chiu, Pi-Feng and Nikolic, Borivoje and Asanovic, Krste}, biburl = {https://www.bibsonomy.org/bibtex/2f4d31dcf9e63b939f992544a2ef0dfcf/dblp}, booktitle = {A-SSCC}, crossref = {conf/asscc/2016}, ee = {https://doi.org/10.1109/ASSCC.2016.7844150}, interhash = {1544ba5f073889b2bff4f4369493cf7e}, intrahash = {f4d31dcf9e63b939f992544a2ef0dfcf}, isbn = {978-1-5090-3700-1}, keywords = {dblp}, pages = {121-124}, publisher = {IEEE}, timestamp = {2024-04-10T21:35:44.000+0200}, title = {Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor.}, url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2016.html#ZimmerCNA16}, year = 2016 }