%0 Conference Paper %1 conf/intelitsis/DrozdBMZD22 %A Drozd, Oleksandr %A Baskov, Illya %A Martynyuk, Oleksandr %A Zashcholkin, Kostiantyn %A Drozd, Myroslav %B IntelITSIS %D 2022 %E Hovorushchenko, Tetiana %E Savenko, Oleg %E Popov, Peter T. %E Lysenko, Sergii %I CEUR-WS.org %K dblp %P 474-483 %T Augmented Checkability of LUT-oriented Circuits in FPGA-based Components of Safety-Related Systems. %U http://dblp.uni-trier.de/db/conf/intelitsis/intelitsis2022.html#DrozdBMZD22 %V 3156

@inproceedings{conf/intelitsis/DrozdBMZD22, added-at = {2023-03-10T00:00:00.000+0100}, author = {Drozd, Oleksandr and Baskov, Illya and Martynyuk, Oleksandr and Zashcholkin, Kostiantyn and Drozd, Myroslav}, biburl = {https://www.bibsonomy.org/bibtex/23734bbc4b5304c27eed61e86c773cd98/dblp}, booktitle = {IntelITSIS}, crossref = {conf/intelitsis/2022}, editor = {Hovorushchenko, Tetiana and Savenko, Oleg and Popov, Peter T. and Lysenko, Sergii}, ee = {https://ceur-ws.org/Vol-3156/paper36.pdf}, interhash = {1679de95af222a48add16c59dcdc49df}, intrahash = {3734bbc4b5304c27eed61e86c773cd98}, keywords = {dblp}, pages = {474-483}, publisher = {CEUR-WS.org}, series = {CEUR Workshop Proceedings}, timestamp = {2024-04-09T19:20:52.000+0200}, title = {Augmented Checkability of LUT-oriented Circuits in FPGA-based Components of Safety-Related Systems.}, url = {http://dblp.uni-trier.de/db/conf/intelitsis/intelitsis2022.html#DrozdBMZD22}, volume = 3156, year = 2022 }