%0 Conference Paper %1 conf/fpga/ZhaZWL17 %A Zha, Yue %A Zhang, Jialiang %A Wei, Zhiqiang %A Li, Jing %B FPGA %D 2017 %E Greene, Jonathan W. %E Anderson, Jason Helge %I ACM %K dblp %P 285 %T A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). %U http://dblp.uni-trier.de/db/conf/fpga/fpga2017.html#ZhaZWL17 %@ 978-1-4503-4354-1

@inproceedings{conf/fpga/ZhaZWL17, added-at = {2020-09-24T00:00:00.000+0200}, author = {Zha, Yue and Zhang, Jialiang and Wei, Zhiqiang and Li, Jing}, biburl = {https://www.bibsonomy.org/bibtex/2df31458589240c89e165948c1f20a954/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2017}, editor = {Greene, Jonathan W. and Anderson, Jason Helge}, ee = {http://dl.acm.org/citation.cfm?id=3021759}, interhash = {17f126a5d26af087202265c5207874e5}, intrahash = {df31458589240c89e165948c1f20a954}, isbn = {978-1-4503-4354-1}, keywords = {dblp}, pages = 285, publisher = {ACM}, timestamp = {2020-09-25T12:04:13.000+0200}, title = {A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only).}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2017.html#ZhaZWL17}, year = 2017 }