%0 Journal Article %1 journals/tvlsi/TaskinH08 %A Taskin, Baris %A Hong, Bo %D 2008 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 12 %P 1648-1656 %T Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#TaskinH08 %V 16

@article{journals/tvlsi/TaskinH08, added-at = {2020-03-11T00:00:00.000+0100}, author = {Taskin, Baris and Hong, Bo}, biburl = {https://www.bibsonomy.org/bibtex/2fb0cf078a3c0c57cac91b5699cc7fe50/dblp}, ee = {https://doi.org/10.1109/TVLSI.2008.2003171}, interhash = {119a0333bad3d9a38f0091d3ea779ea7}, intrahash = {fb0cf078a3c0c57cac91b5699cc7fe50}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 12, pages = {1648-1656}, timestamp = {2020-03-12T11:43:56.000+0100}, title = {Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#TaskinH08}, volume = 16, year = 2008 }