%0 Journal Article %1 journals/jpdc/MartinezCAS12 %A Martínez, Raúl %A Claver, José M. %A Alfaro, Francisco J. %A Sánchez, José L. %D 2012 %J J. Parallel Distributed Comput. %K dblp %N 8 %P 975-989 %T Hardware implementation study of several new egress link scheduling algorithms. %U http://dblp.uni-trier.de/db/journals/jpdc/jpdc72.html#MartinezCAS12 %V 72

@article{journals/jpdc/MartinezCAS12, added-at = {2020-02-22T00:00:00.000+0100}, author = {Martínez, Raúl and Claver, José M. and Alfaro, Francisco J. and Sánchez, José L.}, biburl = {https://www.bibsonomy.org/bibtex/23d2e2eda754ed0e49be75d0f82022ce0/dblp}, ee = {https://doi.org/10.1016/j.jpdc.2012.04.010}, interhash = {1a20d166c5dc55b8e823a14ae709b4e9}, intrahash = {3d2e2eda754ed0e49be75d0f82022ce0}, journal = {J. Parallel Distributed Comput.}, keywords = {dblp}, number = 8, pages = {975-989}, timestamp = {2020-02-25T12:45:51.000+0100}, title = {Hardware implementation study of several new egress link scheduling algorithms.}, url = {http://dblp.uni-trier.de/db/journals/jpdc/jpdc72.html#MartinezCAS12}, volume = 72, year = 2012 }