%0 Journal Article %1 journals/tvlsi/Sanchez-MacianR16 %A Sánchez-Macián, Alfonso %A Reviriego, Pedro %A Maestro, Juan Antonio %D 2016 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 12 %P 3538-3542 %T Optimizing the Implementation of SEC-DAEC Codes in FPGAs. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#Sanchez-MacianR16 %V 24

@article{journals/tvlsi/Sanchez-MacianR16, added-at = {2020-12-29T00:00:00.000+0100}, author = {Sánchez-Macián, Alfonso and Reviriego, Pedro and Maestro, Juan Antonio}, biburl = {https://www.bibsonomy.org/bibtex/2d88cd053fa90271fdfd6e8eb596ecff8/dblp}, ee = {https://doi.org/10.1109/TVLSI.2016.2556943}, interhash = {1c299292ef309d7416e951eab747cb2e}, intrahash = {d88cd053fa90271fdfd6e8eb596ecff8}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 12, pages = {3538-3542}, timestamp = {2024-04-08T14:32:20.000+0200}, title = {Optimizing the Implementation of SEC-DAEC Codes in FPGAs.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#Sanchez-MacianR16}, volume = 24, year = 2016 }