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%0 Conference Paper
%1 conf/fpl/WangCKCG05
%A Wang, Chi-Wei
%A Carter, Nicholas P.
%A Kujoth, Richard B.
%A Cook, Jeffrey J.
%A Gottlieb, Derek B.
%B FPL
%D 2005
%E Rissa, Tero
%E Wilton, Steven J. E.
%E Leong, Philip Heng Wai
%I IEEE
%K dblp
%P 57-64
%T Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.
%U http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#WangCKCG05
%@ 0-7803-9362-7
@inproceedings{conf/fpl/WangCKCG05,
added-at = {2023-03-24T00:00:00.000+0100},
author = {Wang, Chi-Wei and Carter, Nicholas P. and Kujoth, Richard B. and Cook, Jeffrey J. and Gottlieb, Derek B.},
biburl = {https://www.bibsonomy.org/bibtex/2c5cfdd067cd95e748d4014a3e958c7f1/dblp},
booktitle = {FPL},
crossref = {conf/fpl/2005},
editor = {Rissa, Tero and Wilton, Steven J. E. and Leong, Philip Heng Wai},
ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515699},
interhash = {1e20df4e550340e355caf5bae06b7742},
intrahash = {c5cfdd067cd95e748d4014a3e958c7f1},
isbn = {0-7803-9362-7},
keywords = {dblp},
pages = {57-64},
publisher = {IEEE},
timestamp = {2024-04-10T14:52:35.000+0200},
title = {Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.},
url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#WangCKCG05},
year = 2005
}