%0 Conference Paper %1 conf/vlsi/PettenghiCSA10 %A Pettenghi, Héctor %A Chaves, Ricardo %A Sousa, Leonel %A Avedillo, Maria J. %B VLSI-SoC %D 2010 %I IEEE %K dblp %P 119-124 %T An improved RNS generator 2n +/- k based on threshold logic. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2010.html#PettenghiCSA10

@inproceedings{conf/vlsi/PettenghiCSA10, added-at = {2019-06-02T00:00:00.000+0200}, author = {Pettenghi, Héctor and Chaves, Ricardo and Sousa, Leonel and Avedillo, Maria J.}, biburl = {https://www.bibsonomy.org/bibtex/2e8963b249529a96d0bbf8589ab1d6237/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2010soc}, ee = {https://www.wikidata.org/entity/Q59357565}, interhash = {1fa7d91168eedf3262f666b78bfad08c}, intrahash = {e8963b249529a96d0bbf8589ab1d6237}, keywords = {dblp}, pages = {119-124}, publisher = {IEEE}, timestamp = {2019-06-04T14:10:33.000+0200}, title = {An improved RNS generator 2n +/- k based on threshold logic.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2010.html#PettenghiCSA10}, year = 2010 }