%0 Conference Paper %1 conf/apccas/HuangZLCT18 %A Huang, Huajie %A Zeng, Yanhan %A Liao, Jinrui %A Chen, Rongjun %A Tan, Hong-Zhou %B APCCAS %D 2018 %I IEEE %K dblp %P 82-85 %T Performance optimization for the CMOS voltage reference circuit based on NSGA-II. %U http://dblp.uni-trier.de/db/conf/apccas/apccas2018.html#HuangZLCT18 %@ 978-1-5386-8240-1

@inproceedings{conf/apccas/HuangZLCT18, added-at = {2020-06-15T00:00:00.000+0200}, author = {Huang, Huajie and Zeng, Yanhan and Liao, Jinrui and Chen, Rongjun and Tan, Hong-Zhou}, biburl = {https://www.bibsonomy.org/bibtex/20032b2ad8180b33fc072295d1a5fd6d4/dblp}, booktitle = {APCCAS}, crossref = {conf/apccas/2018}, ee = {https://doi.org/10.1109/APCCAS.2018.8605700}, interhash = {235166811a0f63ef5910c435b70de43e}, intrahash = {0032b2ad8180b33fc072295d1a5fd6d4}, isbn = {978-1-5386-8240-1}, keywords = {dblp}, pages = {82-85}, publisher = {IEEE}, timestamp = {2020-06-16T12:21:55.000+0200}, title = {Performance optimization for the CMOS voltage reference circuit based on NSGA-II.}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2018.html#HuangZLCT18}, year = 2018 }