%0 Conference Paper %1 conf/fpl/KanazawaM14 %A Kanazawa, Kenji %A Maruyama, Tsutomu %B FPL %D 2014 %I IEEE %K dblp %P 1-4 %T FPGA acceleration of SAT/Max-SAT solving using variable-way cache. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#KanazawaM14

@inproceedings{conf/fpl/KanazawaM14, added-at = {2017-05-21T00:00:00.000+0200}, author = {Kanazawa, Kenji and Maruyama, Tsutomu}, biburl = {https://www.bibsonomy.org/bibtex/26ee80d2b1ae64852ed6089b90ce1796c/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2014}, ee = {https://doi.org/10.1109/FPL.2014.6927405}, interhash = {237b54b93b5d880d46483cf5ddb4bcac}, intrahash = {6ee80d2b1ae64852ed6089b90ce1796c}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T19:13:37.000+0200}, title = {FPGA acceleration of SAT/Max-SAT solving using variable-way cache.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#KanazawaM14}, year = 2014 }