%0 Conference Paper %1 conf/vlsid/AnanthanarayananRU23 %A Ananthanarayanan, Swetha %A Reniwal, Bhupendra Singh %A Upadhyay, Abhishek %B VLSID %D 2023 %I IEEE %K dblp %P 109-114 %T Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2023.html#AnanthanarayananRU23 %@ 979-8-3503-4678-7

@inproceedings{conf/vlsid/AnanthanarayananRU23, added-at = {2023-04-22T00:00:00.000+0200}, author = {Ananthanarayanan, Swetha and Reniwal, Bhupendra Singh and Upadhyay, Abhishek}, biburl = {https://www.bibsonomy.org/bibtex/2ad36826ce1f8dbc84e0f038b70911607/dblp}, booktitle = {VLSID}, crossref = {conf/vlsid/2023}, ee = {https://doi.org/10.1109/VLSID57277.2023.00035}, interhash = {244a4727dc0968a8308fc6e07699067f}, intrahash = {ad36826ce1f8dbc84e0f038b70911607}, isbn = {979-8-3503-4678-7}, keywords = {dblp}, pages = {109-114}, publisher = {IEEE}, timestamp = {2024-04-10T01:04:54.000+0200}, title = {Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2023.html#AnanthanarayananRU23}, year = 2023 }