%0 Conference Paper %1 conf/iscas/LeeLPN10 %A Lee, Jaejun %A Lee, Sungho %A Park, Joontae %A Nam, Sangwook %B ISCAS %D 2010 %I IEEE %K dblp %P 3857-3860 %T Architecture of a multi-slot main memory system for 3.2 Gbps operation. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2010.html#LeeLPN10 %@ 978-1-4244-5309-2

@inproceedings{conf/iscas/LeeLPN10, added-at = {2011-04-14T00:00:00.000+0200}, author = {Lee, Jaejun and Lee, Sungho and Park, Joontae and Nam, Sangwook}, biburl = {https://www.bibsonomy.org/bibtex/2b5aeb7fedb65887718d34bf98c800a10/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2010}, ee = {http://dx.doi.org/10.1109/ISCAS.2010.5537702}, interhash = {264c19c762cf6be2dc51c81f78f374e8}, intrahash = {b5aeb7fedb65887718d34bf98c800a10}, isbn = {978-1-4244-5309-2}, keywords = {dblp}, pages = {3857-3860}, publisher = {IEEE}, timestamp = {2016-05-21T12:21:27.000+0200}, title = {Architecture of a multi-slot main memory system for 3.2 Gbps operation.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2010.html#LeeLPN10}, year = 2010 }