Meta data
- BibTeX key
- conf/ccs/ChenLMZLCW18
- entry type
- inproceedings
- booktitle
- AsiaCCS
- year
- 2018
- pages
- 601-608
- publisher
- ACM
- crossref
- conf/ccs/2018asia
- ee
- https://doi.org/10.1145/3196494.3196501
- url
- http://dblp.uni-trier.de/db/conf/ccs/asiaccs2018.html#ChenLMZLCW18
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- please select -%0 Conference Paper
%1 conf/ccs/ChenLMZLCW18
%A Chen, Sanchuan
%A Liu, Fangfei
%A Mi, Zeyu
%A Zhang, Yinqian
%A Lee, Ruby B.
%A Chen, Haibo
%A Wang, XiaoFeng
%B AsiaCCS
%D 2018
%E Kim, Jong
%E Ahn, Gail-Joon
%E Kim, Seungjoo
%E Kim, Yongdae
%E López, Javier
%E Kim, Taesoo
%I ACM
%K dblp
%P 601-608
%T Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses.
%U http://dblp.uni-trier.de/db/conf/ccs/asiaccs2018.html#ChenLMZLCW18
@inproceedings{conf/ccs/ChenLMZLCW18,
added-at = {2020-09-01T00:00:00.000+0200},
author = {Chen, Sanchuan and Liu, Fangfei and Mi, Zeyu and Zhang, Yinqian and Lee, Ruby B. and Chen, Haibo and Wang, XiaoFeng},
biburl = {https://www.bibsonomy.org/bibtex/211077bf04bc2d335eb4b4385f91dd376/dblp},
booktitle = {AsiaCCS},
crossref = {conf/ccs/2018asia},
editor = {Kim, Jong and Ahn, Gail-Joon and Kim, Seungjoo and Kim, Yongdae and López, Javier and Kim, Taesoo},
ee = {https://doi.org/10.1145/3196494.3196501},
interhash = {2b2cccf57c2ca1b758f05ec34acc7281},
intrahash = {11077bf04bc2d335eb4b4385f91dd376},
keywords = {dblp},
pages = {601-608},
publisher = {ACM},
timestamp = {2020-11-11T11:39:16.000+0100},
title = {Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses.},
url = {http://dblp.uni-trier.de/db/conf/ccs/asiaccs2018.html#ChenLMZLCW18},
year = 2018
}