%0 Conference Paper %1 conf/apccas/MiyaokaCTYO02 %A Miyaoka, Yuichiro %A Choi, Jinku %A Togawa, Nozomu %A Yanagisawa, Masao %A Ohtsuki, Tatsuo %B APCCAS (1) %D 2002 %I IEEE %K dblp %P 171-176 %T An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. %U http://dblp.uni-trier.de/db/conf/apccas/apccas2002-1.html#MiyaokaCTYO02 %@ 0-7803-7690-0

@inproceedings{conf/apccas/MiyaokaCTYO02, added-at = {2007-12-20T00:00:00.000+0100}, author = {Miyaoka, Yuichiro and Choi, Jinku and Togawa, Nozomu and Yanagisawa, Masao and Ohtsuki, Tatsuo}, biburl = {https://www.bibsonomy.org/bibtex/23f9d374fbc42663fe539260ea141e231/dblp}, booktitle = {APCCAS (1)}, crossref = {conf/apccas/2002}, ee = {http://dx.doi.org/10.1109/APCCAS.2002.1114930}, interhash = {2ef6bb3ebaa59a849f36b800aaf2c262}, intrahash = {3f9d374fbc42663fe539260ea141e231}, isbn = {0-7803-7690-0}, keywords = {dblp}, pages = {171-176}, publisher = {IEEE}, timestamp = {2015-06-19T04:11:09.000+0200}, title = {An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2002-1.html#MiyaokaCTYO02}, year = 2002 }